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The Clock Domains and Reset Domains tabs also allow you to locate system performance bottlenecks. The tabs indicate connection points where Platform Designer automatically inserts clock-crossing adapters and reset synchronizers during system generation.
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Note: ModelSim* - Intel® FPGA Edition supports native, mixed-language (VHDL/Verilog/SystemVerilog) simulation. Therefore, Intel simulation libraries may not be compatible with single language simulators. If you have a VHDL-only license, some versions of ModelSim* simulators may not support simulation for IPs written in Verilog. As a workaround, you can use ModelSim* - Intel® FPGA Edition, or purchase a mixed language simulation license from Mentor.
Wire-level connectivity enables you to manipulate wire-level connections in the system level view of Platform Designer. For example, you can enter a Verilog style syntax expression to drive an input port of an IP component.
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Note: If certain adapters or IP components are not present in the interconnect, or if there are not enough pipelineable locations in the interconnect, Platform Designer does not add all of the pipeline stages specified. Click Show System with Interconnect to view the number of stages added for a particular domain.
Click Highlight Mode (Path, Successors, Predecessors) to identify edges and datapaths between modules. Turn on Show Pipelinable Locations to add greyed-out registers on edges where pipelining is allowed in the interconnect.
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Otherwise this field is non-editable and displays the Quartus project target device family. Click Retrieve Values to populate the fields.
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Each node element in a figure represents either a host or agent that communicates over the interconnect, or an interconnect sub-module. Each edge is an abstraction of connectivity between elements, and its direction represents the flow of the commands or responses.
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You can specify between 0 and 4 as the maximum number of pipeline stages to insert. The default value is 1. A value of 0 indicates no pipelines and a combinational datapath. When you specify 1 or greater, Platform Designer inserts up to the number you specify, depending on availability of pipeline locations.
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To perform system integrity check for the entire system, click the Validate System Integrity button at the bottom of main Platform Designer window. If validation finds errors, click Reload and Update All Components to reload signal and interface values from the corresponding IP component file.
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After you define wire-level expressions, generate the system to create the Verilog files. When the Platform Designer GUI or qsys-script utility applies the expression, the expression inserts into the Verilog wrapper file that generates for your system.
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Displays internal connections of Platform Designer subsystems that you include as IP components. By contrast, the System View tab displays only the exported interfaces of Platform Designer subsystems.
Click inside an open connection circle to implement the connection between the interfaces. When you make a connection, Platform Designer changes the connection line to black, and fills the connection circle. Clicking a filled-in circle removes the connection.
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If you make changes to your system, Platform Designer prompts you to generate your system before closing. Generate your system to ensure that the Compiler includes any changes you make to your system.
The testbench generator supports AXI interfaces and can connect AMBA* 3 AXI or AMBA* 3 AXI interfaces to Mentor Graphics AMBA* 3 AXI or AMBA* 3 AXI master/slave BFMs. However, BFMs support address widths only up to 32-bits.
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If you open a Platform Designer system with incompatible components, Platform Designer prompts you to convert these components to the current Platform Designer format. On conversion, the Platform Designer Conversion Results dialog box appears, listing all the converted system and IP source files.
The Domains tab displays the Avalon memory mapped interfaces in your system, and allows you to specify legal values for available system-level or interface parameters. While specifying parameters, you can click Show System with Interconnect to view a schematic preview of the Platform Designer complete system interconnect.
For example, you can connect a memory-mapped host interface to an agent interface, and an interrupt sender interface to an interrupt receiver interface. You can connect any interfaces exported from a Platform Designer system within a parent system.
You can add third-party IP components created by Intel partners to your Platform Designer system. Third-party partner IP components have interfaces that Platform Designer supports, such as Avalon® memory mapped or AMBA* AXI. Third-party partner IP components can also include timing and placement constraints, software drivers, simulation models, and reference designs.
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Parallel IP generation derives the maximum number of processors to use from the Maximum processors allowed Compiler setting. If you specify no value for this setting, the Intel® Quartus® Prime software selects an appropriate number based on the available processors, and the number of tasks the processors can execute in parallel.
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The Interface Requirements tab allows you to assign a component's top-level HDL module signals to an interface, specify the expected signal and interface boundary requirements for the interface, and to resolve any interface requirement mismatches. You can also modify the signal names in an exported interface.
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Access to an undefined memory region occurs when a transaction from a master targets a memory region unspecified in the slave memory map. To ensure predictable response behavior when this condition occurs, you must specify a default slave, as Specifying a Default Slave describes.
Select individual interfaces, signals, or parameters to view the specific value differences in the Component and IP file columns. Value mismatches between the Component Instantiation and the IP file appear in blue.
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You can modify the name of the exported signal or interface from this table. For more information about how to edit the name of an exported signal or interface, refer to Edit the Name of Exported Interfaces and Signals.
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The Avalon® specification does not include a protection signal. Consequently, when an Avalon® host sends a command, there is no embedded security and Platform Designer recognizes the command as non-secure. Similarly, when an Avalon® agent receives a command, the agent always accepts the command and responds.
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You can connect two conduits directly within a Platform Designer system as a point-to-point connection. Alternatively, you can export conduit interfaces and bring the interfaces to the top-level of the system as top-level system I/O. You can use conduits to connect to external devices, for example external DDR SDRAM memory, and to FPGA logic defined outside of the Platform Designer system.
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You can achieve an optimized secure system by partitioning your design and carefully designating secure or non-secure address maps to maintain reliable data. Avoid a design that includes a non-secure AXI master that initiates transactions to a secure slave resulting in unsuccessful transfers, within the same hierarchy.
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All softwares are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
System Console reads this section, which Platform Designer can query for register map information. For system agents, Platform Designer can access the registers by name.
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If you have a project open, this project name appears automatically. Otherwise, browse for an existing project, or click the Create New Quartus Project button and specify a new project name.
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You can designate any memory-mapped slave as a default slave. Have only one default slave for each interconnect domain in your system. Platform Designer then routes undefined memory region accesses to the default slave, which terminates the transaction with an error response.
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The Block Symbol tab displays a symbolic representation of any component you select in the Hierarchy or System View tabs. The block symbol shows the component's port interfaces and signals. The Show signals option allows you to turn on or off signal graphics.
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Assert the reset for at least 16 cycles and start transactions 16 cycles after deassertion of the reset. This period allows all the IP components to reset and come out of the reset state. To avoid deadlocks in the interconnect, reset masters and agents simultaneously. If masters and agents have different resets, agents must reset only after responding to all necessary transactions. The Use synchronous reset option is enabled by default for Intel® Hyperflex™ architecture devices, but is disabled by default for all other devices. Enabling synchronous reset for the interconnect does not enable synchronous reset for IP components in the system.
Under Parallel IP Generation, enable or disable the Enable parallel generation of Quartus IPs in all projects option. When enabled, the Intel® Quartus® Prime software uses multiple processors (if available in your system) for faster IP generation.
The latency of the FIFO-based adapter is a couple of clock cycles more than the handshaking clock crossing component. However, the FIFO-based adapter can sustain higher throughput because it supports multiple transactions at any given time. FIFO-based clock crossing adapters require more resources. The FIFO adapter is appropriate for memory-mapped transfers requiring high throughput across clock domains.
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